Second Semester_Digital Logic_VHDL

 

7.1 RTL Design with VHDL

• RTL (Register Transfer Level) = designing circuits at the level of registers and how data moves between them.

• VHDL is a language used to describe hardware behavior.
  

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7.1.1 Shape of VHDL

• VHDL code has 3 main parts:

  1. Library/Use → bring in standard tools.

  2. Entity → defines inputs/outputs (like a blueprint).

  3. Architecture → defines behavior (how circuit works).

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7.1.2 Data Types

• Common VHDL types:

  • bit → 0 or 1

  • std_logic → 0,1,Z,X (more realistic for hardware)

  • integer → numbers

  • boolean → TRUE or FALSE

  • array → multiple bits together

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7.1.3 Concurrent Statements

• Statements that run at the same time, like wiring in hardware.

• Example: y <= a AND b; runs continuously, not step by step.

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7.1.4 Processes and Variables

• Process → sequential block inside VHDL, runs when triggered by signals.

• Variable → temporary storage inside a process (changes immediately)

• Signal → storage that updates after the process ends.

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7.1.5 Simulating a Simple Design

• Testing your design in software before hardware.

• You create a testbench to see if your circuit works.

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7.1.6 Creating Memory

• RAM/ROM can be made using arrays.

• Example: type memory_array is array (0 to 15) of std_logic_vector(7 downto 0);

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7.1.7 Finite State Machines (FSM)

• FSM = circuit with states and transitions.

• 3 parts:

  1. State register → holds current state

  2. Next state logic → decides next state

  3. Output logic → produces output based on state

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7.1.8 Loops and Conditional Elaboration

• If-Else / Case → choose actions

• For/While loops → repeat actions

• Helps generate repetitive hardware easily.

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7.1.9 Attributes

• Extra info about signals or types, like:

  • 'length → number of bits

  • 'range → valid range of array

  • 'high/'low → highest/lowest value

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7.1.10 Functions and Procedures

• Function → returns a value, used in expressions

• Procedure → performs tasks, doesn’t return a value

• Helps reuse code and keeps it neat.

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✅ TL;DR:

• Entity = interface, Architecture = behavior

• Signals = hardware wires, Variables = inside process

• Concurrent = all together, Sequential = inside process

• FSM = states + transitions, Loops & conditionals = repeat/check

• Functions & procedures = reusable code