Second Semester_Digital Logic_Sequential Circuit Design
5.1 Flip-Flops: RS, JK, D, and T, Latches
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Flip-Flops: Bistable devices that store 1 bit of data. They have two stable states.
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RS (Set-Reset) Flip-Flop:
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Inputs: R (Reset), S (Set)
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Output Q = 1 when S=1, Q=0 when R=1
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JK Flip-Flop:
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Inputs: J, K
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Toggle behavior: If J=K=1, output toggles
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Solves invalid state problem of RS flip-flop
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D Flip-Flop (Data/Delay):
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Input: D
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Output follows D at clock edge (avoids race conditions)
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T Flip-Flop (Toggle):
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Input: T
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Toggles output when T=1 at clock edge
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Used in counters
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Latches: Level-triggered storage devices (respond to input levels, not clock edges).
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Types: SR latch, D latch
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5.2 Triggering of Flip-Flops
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Level Triggered: Flip-flop changes state as long as clock is active. (Risk of multiple transitions)
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Edge Triggered: Flip-flop changes state only at the rising or falling edge of the clock.
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More reliable for synchronous designs.
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5.3 Master-Slave Flip-Flop
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Combines two flip-flops in series: Master and Slave
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Master responds to clock pulse, slave responds to inverted clock
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Ensures edge-triggered behavior and prevents race conditions.
5.4 Flip-Flop Excitation Table and Design Procedure
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Excitation Table: Tells what input values are needed to make a flip-flop go from current state to next state.
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Example: JK flip-flop excitation table:
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| Current Q | Next Q | J | K |
|---|---|---|---|
| 0 | 0 | 0 | X |
| 0 | 1 | 1 | X |
| 1 | 0 | X | 1 |
| 1 | 1 | X | 0 |
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Design Procedure:
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Define states and inputs.
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Draw state table or state diagram.
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Select flip-flop type.
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Use excitation table to determine flip-flop inputs.
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Derive logic equations and implement circuit.
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5.5 State Diagram and Simple Sequential Circuits
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State Diagram: Graphical representation of states (circles) and transitions (arrows) based on inputs.
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Simple Sequential Circuit: Implement a design where outputs depend on current input + previous state.
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Example: Traffic light controller, sequence detector.
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